In general, aluminum and aluminum alloy thins film have been widely used as metal line material for semiconductor circuits due to their high conductivity, ease of patterning by dry etching, and excellent adhesion to silicon oxide film, as well as their low cost.
However, as packing densities of semiconductor integrated circuits increase, the sizes of the semiconductor devices have decreased and the metal lines therein have become increasingly more fine and multilayered. In this regard, problems associated with step coverage have become significant for portions of the semiconductor device having a nonplanar or stepped surface, such as a via hole (a hole exposing a conductor as opposed to a contact hole that exposes a semiconductor) or a contact hole.
In a method for forming a metal line using conventional sputtering, the portion of the metal line layer formed on the region having a nonplanar surface becomes thinner due to the shadow effect. In particular, the thickness of the metal line layer becomes significantly thinner at a via hole having aspect ratio (AR) of 1 or more, where AR=(hole height)/(hole diameter)=(hole height)/(hole width in cross section).
Accordingly, instead of a physical deposition like sputtering (which imparts random direction and significant magnitude velocities to the atoms being deposited), the conventional art has relied on the chemical vapor deposition (CVD) method, which is capable of depositing the metal line layer at a uniform thickness. The CVD method produces atoms having random direction velocities, albeit with much lower magnitudes. In order to improve step coverage, a tungsten layer has been formed by using low pressure chemical vapor deposition (LPCVD) . However, since the tungsten layer has resistivity two or more times as great as compared to an aluminum layer, it is difficult for the tungsten layer to be applied to the conducting layer.
For this reason, a method for forming a metal line, having a separately formed plug layer in a via hole, has been developed. The plug layer is formed by using CVD to selectively grow a tungsten layer on an exposed substrate in the via hole. Alternatively, formation of the plug layer is preceded by first forming a barrier metal layer or a glue layer, and then depositing a tungsten layer thereon and etching it back by an amount that is greater than its deposition thickness (to produce a plug layer not extending outside the via hole).
However, it is difficult to grow the tungsten layer in the via hole without also growing it on an insulating film, i.e., the selectivity of tungsten between the exposed material in the via hole and the insulation film is not a high value. Also, the other technology requires that a reliable barrier layer or glue layer be formed in the via hole having a high aspect ratio. Here, it is essential that the barrier layer or the glue layer has a minimum thickness sufficient to promote nucleation of the tungsten layer at the bottom and sidewalls of the via hole thus requiring the use of a collimator when sputtering or the use of CVD.
The depth of the via hole depends on the degree of planarization of the insulating film in which the via hole is formed. A depth of the via hole will be different from that of the plug layer because of the varying planarization of the hole. That is, the surface of the plug layer substantially becomes lower than that of the via hole.
Aluminum reflow can be achieved in two ways, by heat treating the aluminum after it is deposited by way of normal temperature or by sputtering at high temperature. For high temperature sputtering, the temperature of the substrate is raised to around 500.degree. C. to thus increase fluidness of an aluminum particle so that the aluminum particle flows to the via hole. Before depositing the aluminum, a lower layer (such as Ti, TiN or stacked arrangement thereof) is used for high adhesion of the aluminum. Aluminum may suffer undesirable step coverage as well as exhibit undesirable surface conditions. For this reason, a void may occur in the via hole or a disconnection may occur at the sides of the via hole.
In the other conventional method for forming a metal line, a conductivity layer of low resistance is deposited by CVD into the via hole to improve step coverage in the via hole. Low resistance materials such as aluminum, Cu and Au are used to be the conductivity layer. The materials DMAH (Dimethylalumiumhydride) or DMEAA (Dimethylethylaminalane) may be used as sources for aluminum, while the material (hafc)Cu(TMVS) may be used as a source for Cu.
However, in the latter conventional method, in general, a surface of a CVD-formed thin film is significantly rough. Thus, in the case that a CVD thin film of 0.5 .mu.m or less is used as a conductive line, it is difficult to pattern the CVD thin film because the reflectivity of the conductive line is low. Also in such a film electromigration occurs much more easily.
The conventional method for forming a metal line of a semiconductor device will be described with reference to the accompanying drawings.
FIG. 1a to FIG. 1d are sectional views of a metal line of a conventional semiconductor device. FIG. 2a and FIG. 2b are sectional views of a metal line of another conventional semiconductor device.
FIG. 1a to FIG. 1d shows process steps for forming an upper conductive line after forming a tungsten plug layer so as to connect a lower conductive line with the upper conductive line. As shown in FIG. 1a, a lower insulating film 2 is formed on a semiconductor substrate 1 and a lower conductive line 3 is formed on the lower insulating film 2. Subsequently, an upper insulating film 4 is formed on the exposed surfaces (including the lower conductive line 3) and then etched to selectively expose the lower layer line 3, so that a via hole 5 is formed.
As shown in FIG. 1b, a barrier layer 6 is formed on the exposed surfaces including the lower conductive line 3 and sides of the via hole 5. On the barrier layer 6, a first conductive material layer 7 is formed.
The first conductivity material layer 7 and the barrier layer 6 are etched back to form a plug layer 8 in the via hole 5, as shown in FIG. 1c. Here, the first conductivity material layer 7 is overly etched back to completely remove materials remaining on portions of the insulating layer away from the via hole where step coverage occurs.
As shown in FIG. 1d, a second conductive material layer 9 is formed on the exposed surfaces including the via hole 5 and the plug layer 8 therein. The second conductivity material layer 9 is then patterned to form an upper layer line.
FIG. 2a to FIG. 2b shows process steps for forming an upper layer line without additionally forming a plug layer (i.e., a plug layer would lower resistivity between the lower line and the upper line) and, at the same time, for filling the via hole.
As shown in FIG. 2a, a lower insulating film 2 is formed on a semiconductor substrate 1. A lower conductive line 3 is formed on the lower insulating film 2. Subsequently, an upper insulating film 4 is formed on the exposed surfaces including the lower layer line 3 and etched to selectively expose the lower layer line 3 so that a via hole 5 is formed.
As shown in FIG. 2b, a barrier layer 6 is formed on the exposed surfaces including the lower conductive line 3 and sides of the via hole 5. A conductive material layer 7 is CVD deposited on the barrier layer 6 to fill the via hole 5 and then is patterned to form an upper layer line. This simplifies the process steps because the upper layer line is formed by filling the via hole without separately forming the plug layer.
However, the conventional method for forming a metal line of a semiconductor device has several problems.
First, in the case that the plug layer is formed by etch back process according to selective deposition or blanket deposition of tungsten (in order to improve step coverage of the conductivity material layer at the via hole), a glue layer such as Ti, TiN, or TiW should be formed in the via hole to promote nucleation i.e., growth of the plug layer. In addition, resistivity of the plug layer becomes high, namely 5 .mu..OMEGA./cm or above. The glue layer must have a minimum thickness capable of adequately promoting nucleation of the tungsten. For this, a collimator or CVD process is required.
In the case that the via hole is filled while forming an upper layer line for low resistivity in the via hole as shown in FIG. 2, the via hole is filled and at the same time the conductive line is formed by CVD process. In this case, a surface of the conductive line is rough so that reliability of the metal line is reduced.